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2.5 v to 5.5 v, 500 a, quad voltage output 8-/10-/12-bit dacs in 10-lead packages data sheet ad5304 / ad5314 / ad5324 rev. h information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features ad5304: 4 buffered 8-bit dacs in 10-lead msop and 10-lead lfcsp a, w version: 1 lsb inl, b version: 0.625 lsb inl ad5314: 4 buffered 10-bit dacs in 10-lead msop and 10-lead lfcsp a, w version: 4 lsb inl, b version: 2.5 lsb inl ad5324: 4 buffered 12-bit dacs in 10-lead msop and 10-lead lfcsp a, w version: 16 lsb inl, b version: 10 lsb inl low power operation: 500 a @ 3 v, 600 a @ 5 v 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 80 na @ 3 v, 200 na @ 5 v double-buffered input logic output range: 0 v to v ref power-on reset to 0 v simultaneous update of outputs ( ldac function) low power-, spi?-, qspi?-, microwire?-, and dsp- compatible 3-wire serial interface on-chip, rail-to-rail output buffer amplifiers temperature range ?40c to +105c qualified for automotive applications applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process controls general description the ad5304 / ad5314/ ad5324 1 are quad 8-, 10-, and 12-bit buffered voltage output dacs in 10-lead msop and 10-lead lfcsp packages that operate from a single 2.5 v to 5.5 v supply, consuming 500 a at 3 v. their on-chip output amplifiers allow rail-to-rail output swing to be achieved with a slew rate of 0.7 v/s. a 3-wire serial interface is used; it operates at clock rates up to 30 mhz and is compatible with standard spi, qspi, microwire, and dsp interface standards. the references for the four dacs are derived from one reference pin. the outputs of all dacs can be updated simultaneously using the software ldac function. the parts incorporate a power-on reset circuit, and ensure that the dac outputs power up to 0 v and remains there until a valid write takes place to the device. the parts contain a power-down feature that reduces the current consumption of the device to 200 na @ 5 v (80 na @ 3 v). the low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. the power consumption is 3 mw at 5 v, 1.5 mw at 3 v, reducing to 1 w in power-down mode. 1 protected by u.s. patent no. 5,969,657. functional block diagram input register dac register string dac a v out a buffer input register dac register string dac b v out b buffer ad5304/ad5314/ad5324 input register dac register string dac c v out c buffer input register dac register string dac d v out d buffer refin v dd gnd power-down logic power-on reset ldac interface logic sclk sync din 00929-001 figure 1.
ad5304/ad5314/ad5324 data sheet rev. h | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ac characteristics ........................................................................ 4 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 8 ? terminology .................................................................................... 12 ? theory of operation ...................................................................... 14 ? functional description .............................................................. 14 ? power-on reset .......................................................................... 14 ? serial interface ............................................................................ 14 ? power-down mode .................................................................... 16 ? microprocessor interfacing ....................................................... 16 ? applications information .............................................................. 18 ? typical application circuit ....................................................... 18 ? decoding multiple ad5304/ad5314/ad5324s .................... 19 ? power supply bypassing and grounding ................................ 20 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 23 ? automotive products ................................................................. 23 ? revision history 9/11rev. g to rev. h changes to table 4 ............................................................................ 6 5/11rev. f to rev. g added w versio n ............................................................... universal added epad notation to figure 4 ................................................. 7 updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 23 added automotive products section .......................................... 23 9/06rev. e to rev. f updated format .................................................................. universal changes to specifications section .................................................. 3 changes to table 5 ............................................................................ 7 updated outline dimensions ...................................................... 22 changes to ordering guide .......................................................... 23 5/05rev. d to rev. e added 10-lead lfcsp package ......................................... universal changes to title ................................................................................ 1 changes to ordering guide ............................................................ 4 8/03rev. c to rev. d added a version ................................................................ universal changes to features .......................................................................... 1 changes to specifications ................................................................. 2 changes to absolute maximum ratings ........................................ 4 changes to ordering guide ............................................................. 4 changes to figure 6 ........................................................................ 11 added octals section to table 2 .............................................. 15 updated outline dimensions ....................................................... 16
data sheet ad5304/ad5314/ad5324 rev. h | page 3 of 24 specifications v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 1. parameter 1 a, w version 2 b version 2 min typ max min typ max unit test conditions/comments dc performance 3, 4 ad5304 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.625 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5314 resolution 10 10 bits relative accuracy 0.5 4 0.5 2.5 lsb differential nonlinearity 0.05 0.5 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5324 resolution 12 12 bits relative accuracy 2 16 2 10 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 0.4 3 % of fsr see figure 2 and figure 3 gain error 0.15 1 0.15 1 % of fsr see figure 2 and figure 3 lower dead band 20 60 20 60 mv lower dead band exists only if offset error is negative offset error drift 5 C12 C12 ppm of fsr/c gain error drift 5 C5 C5 ppm of fsr/c dc power supply rejection ratio 5 C60 C60 db v dd = 10% dc crosstalk 5 200 200 v r l = 2 k to gnd or v dd dac reference inputs 5 v ref input range 0.25 v dd 0.25 v dd v v ref input impedance 37 45 37 45 k normal operation >10 >10 m power-down mode reference feedthrough C90 C90 db frequency = 10 khz output characteristics 5 minimum output voltage 6 0.001 0.001 v measurement of the minimum and maximum maximum output voltage 6 v dd C 0.001 v dd C 0.001 v drive capability of the output amplifier dc output impedance 0.5 0.5 short circuit current 25 25 ma v dd = 5 v 16 16 ma v dd = 3 v power-up time 2.5 2.5 s coming out of power- down mode v dd = 5 v 5 5 s coming out of power- down mode v dd = 3 v
ad5304/ad5314/ad5324 data sheet rev. h | page 4 of 24 parameter 1 a, w version 2 b version 2 min typ max min typ max unit test conditions/comments logic inputs 5 input current 1 1 a v il , input low voltage 0.8 0.8 v v dd = 5 v 10% 0.6 0.6 v v dd = 3 v 10% 0.5 0.5 v v dd = 2.5 v v ih , input high voltage 2.4 2.4 v v dd = 5 v 10% 2.1 2.1 v v dd = 3 v 10% 2.0 2.0 v v dd = 2.5 v pin capacitance 3 3 pf power requirements v dd 2.5 5.5 2.5 5.5 v i dd (normal mode) 7 v dd = 4.5 v to 5.5 v 600 900 600 900 a v ih = v dd and v il = gnd v dd = 2.5 v to 3.6 v 500 700 500 700 a v ih = v dd and v il = gnd i dd (power-down mode) v dd = 4.5 v to 5.5 v 0.2 1 0.2 1 a v ih = v dd and v il = gnd v dd = 2.5 v to 3.6 v 0.08 1 0.08 1 a v ih = v dd and v il = gnd 1 see the terminology section. 2 temperature range (a, b, w version): ?40c to +105c; typical at +25c. 3 dc specifications tested with the outputs unloaded. 4 linearity is tested using a reduced code range: ad5304 (code 8 to code 248); ad5314 (code 28 to code 995); ad5324 (code 115 to code 3981). 5 guaranteed by design and characterization, not production tested. 6 for the amplifier output to reach its minimum voltage, offset error must be negative. for the amplifier output to reach its ma ximum voltage, v ref = v dd and offset plus gain error must be positive. 7 i dd specification is valid for all dac codes; interface inactive; all dacs active; load currents excluded. ac characteristics v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. parameter 1, 2 a, b, w version 3 min typ max unit test conditions/comments output voltage settling time v ref = v dd = 5 v ad5304 6 8 s ? scale to ? scale change (0x40 to 0xc0) ad5314 7 9 s ? scale to ? scale change (0x100 to 0x300) ad5324 8 10 s ? scale to ? scale change (0x400 to 0xc00) slew rate 0.7 v/ s major-code transition glitch energy 12 nv-sec 1 lsb change around major carry digital feedthrough 1 nv-sec digital crosstalk 1 nv-sec dac-to-dac crosstalk 3 nv-sec multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p total harmonic distortion C70 db v ref = 2.5 v 0.1 v p-p; frequency = 10 khz 1 see the terminology section. 2 guaranteed by design and characterization, not production tested. 3 temperature range (a, b, w version): ?40c to + 105c; typical at +25c.
data sheet ad5304/ad5314/ad5324 rev. h | page 5 of 24 timing characteristics v dd = 2.5 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 3. parameter 1, 2, 3 limit at t min , t max v dd = 2.5 v to 3.6 v v dd = 3.6 v to 5.5 v unit test conditions/comments t 1 40 33 ns min sclk cycle time t 2 16 13 ns min sclk high time t 3 16 13 ns min sclk low time t 4 16 13 ns min sync to sclk falling edge setup time t 5 5 5 ns min data setup time t 6 4.5 4.5 ns min data hold time t 7 0 0 ns min sclk falling edge to sync rising edge t 8 80 33 ns min minimum sync high time 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with tr = tf = 5 ns (10% to 90 % of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figure 2. sclk din db15 db0 t 1 t 3 t 2 t 7 t 5 t 4 t 6 t 8 sync 00929-002 figure 2. serial interface timing diagram
ad5304/ad5314/ad5324 data sheet rev. h | page 6 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter 1 rating v dd to gnd C0.3 v to +7 v digital input voltage to gnd C0.3 v to v dd + 0.3 v reference input voltage to gnd C0.3 v to v dd + 0.3 v v out a through v out d to gnd C0.3 v to v dd + 0.3 v operating temperature range industrial (a, b, w version) C40c to +105c storage temperature range C65c to +150c junction temperature (t j max) 150c 10-lead msop power dissipation (t j max C t a )/ ja ja thermal impedance 206c/w jc thermal impedance 44c/w 10-lead lfcsp power dissipation (t j max C t a )/ ja ja thermal impedance 84c/w reflow soldering peak temperature (pb-free) 260c peak temperature (non pb-free) 220c time at peak temperature 10 sec to 40 sec 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad5304/ad5314/ad5324 rev. h | page 7 of 24 pin configurations and function descriptions v dd 1 v out a 2 v out b 3 v out c 4 refin 5 ad5304/ ad5314/ ad5324 top view (not to scale) sync 10 sclk 9 din 8 gnd 7 v out d 6 0 0929-003 figure 3. 10-lead ms op pin configuration v dd v out a v out b v out c refin ad5304/ ad5314/ ad5324 notes 1. the exposed pad is the ground reference poin t for all circuitry on the part. it can be connected to 0 v or left unconnected provided there is a connection to 0 v via the gnd pin. top view (not to scale) sclk din gnd v out d sync 1 2 3 4 5 00929-004 10 9 8 7 6 figure 4. 10-lead lfcsp pin configuration table 5. pin function descriptions pin no. mnemonic description 1 v dd power supply input. these parts can be operated from 2.5 v to 5.5 v and the supply can be decoupled to gnd. 2 v out a buffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 3 v out b buffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 4 v out c buffered analog output voltage from dac c. the output amplifier has rail-to-rail operation. 5 refin reference input pin for all four dacs. it has an input range from 0.25 v to v dd . 6 v out d buffered analog output voltage from dac d. the output amplifier has rail-to-rail operation. 7 gnd ground reference point for all circuitry on the part. 8 din serial data input. this device has a 16-bit shift register. da ta is clocked into the register on the falling edge of the serial clock input. the din input buffer is powered down after each write cycle. 9 sclk serial clock input. data is clocked into the input shift register on the falling ed ge of the serial clock input. data can be transferred at clock speeds up to 30 mhz. the sclk input buffer is powered down after each write cycle. 10 sync active low control input. this is the frame sy nchronization signal for the input data. when sync goes low, it enables the input shift register and data is transferred in on the falling ed ges of the following 16 clocks. if sync is taken high before the 16 th falling edge of sclk, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. exposed paddle 1 ground reference point for all circuitry on the part. can be connected to 0 v or left unconnected provided there is a connection to 0 v via the gnd pin. 1 for the 10-lead lfcsp only.
ad5304/ad5314/ad5324 data sheet rev. h | page 8 of 24 typical performance characteristics 1.0 0.5 0 ?0.5 ?1.0 0 50 100 150 200 250 inl error (lsb) code t a = 25c v dd = 5v 00929-005 figure 5. ad5304 typical inl plot 3 0 ?1 ?3 2 1 ?2 0 200 400 600 800 1000 inl error (lsb) code t a = 25c v dd = 5v 00929-006 figure 6. ad5314 typical inl plot 12 0 ?4 ?12 8 4 ?8 0 500 1000 1500 2000 2500 3000 3500 4000 inl error (lsb) code t a = 25c v dd = 5v 00929-007 figure 7. ad5324 typical inl plot 0.3 0.1 0 ?0.2 0.2 ?0.1 ?0.3 0 50 100 150 200 250 dnl error (lsb) code t a = 25c v dd = 5v 00929-008 figure 8. ad5304 typical dnl plot 0.6 0.2 0 ?0.4 0.4 ?0.2 ?0.6 0 200 400 600 800 1000 dnl error (lsb) code t a = 25c v dd = 5v 00929-009 figure 9. ad5314 typical dnl plot 1.0 0 ?1.0 0.5 ?0.5 0 500 1000 1500 2000 2500 3000 3500 4000 dnl error (lsb) code t a = 25c v dd = 5v 00929-010 figure 10. ad5324 typical dnl plot
data sheet ad5304/ad5314/ad5324 rev. h | page 9 of 24 0.50 0 ?0.50 0.25 ?0.25 012345 error (lsb) v ref (v) t a = 25c v dd = 5v max inl max dnl min inl min dnl 00929-011 figure 11. ad5304 inl and dnl error vs. v ref 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?40 120 80 40 0 error (lsb) temperature (c) max inl max dnl min inl min dnl v dd = 5v v ref = 3v 00929-012 figure 12. ad5304 inl error and dnl error vs. temperature 1.0 ?1.0 ?0.5 0 0.5 ?40 120 80 40 0 error (%) temperature (c) v dd = 5v v ref = 2v gain error offset error 00929-013 figure 13. ad5304 offset error and gain error vs. temperature 0.2 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 06 5 4 3 2 1 error (%) v dd (v) gain error offset error t a = 25c v ref = 2v 00929-014 figure 14. offset error and gain error vs. v dd 5 0 4 3 2 1 06 5 4 3 2 1 v out (v) sink/source current (ma) 5v source 3v source 5v sink 3v sink 00929-015 figure 15. v out source and sink current capability 600 500 400 300 200 100 0 zero scale full scale i dd (a) code t a = 25c v dd = 5v v ref = 2v 00929-016 figure 16. supply current vs. dac code
ad5304/ad5314/ad5324 data sheet rev. h | page 10 of 24 600 500 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i dd (a) v dd (v) ?40c +105c +25c 00929-017 figure 17. supply current vs. supply voltage 0.5 0.4 0.3 0.2 0.1 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i dd (a) v dd (v) ?40c +105c +25c 00929-018 figure 18. power-down current vs. supply voltage 1000 900 800 700 600 500 400 05.0 4.5 4.0 3.53.02.52.01.51.00.5 i dd (a) v logic (v) t a = 25c v dd = 5v v dd = 3v 00929-019 figure 19. supply current vs. logic input voltage ch1 1v, ch2 5v, time base = 1s/div ch2 ch1 t a = 25c v dd = 5v v ref = 5v v out a sclk 0 0929-020 figure 20. half-scale settling (? to ? scale code change) ch1 2v, ch2 200mv, time base = 200s/div ch2 ch1 t a = 25c v dd = 5v v ref = 2v v dd v out a 0 0929-021 figure 21. power-on reset to 0 v ch1 500mv, ch2 5v, time base = 1s/div ch2 ch1 t a = 25c v dd = 5v v ref = 2v v out a sclk 0 0929-022 figure 22. exiting power-down to midscale
data sheet ad5304/ad5314/ad5324 rev. h | page 11 of 24 300 350 400 450 500 550 600 frequency i dd (a) v dd = 3v v dd = 5v 00929-023 figure 23. i dd histogram with v dd = 3 v and v dd = 5 v 2.50 2.47 2.48 2.49 v out (v) 1s/div 00929-024 figure 24. ad5324 major-code transition glitch energy 10 0 ?10 ?20 ?30 ?40 ?50 ?60 10 10m 1m 100k 10k 1k 100 (db) frequency (hz) 00929-025 figure 25. multiplying bandwidth (small-signal frequency response) 0.02 0.01 0 ?0.01 ?0.02 06 5 4 3 2 1 full-scale error (v) v ref (v) v dd = 5v t a = 25c 00929-026 figure 26. full-scale error vs. v ref 1mv/di v 150ns/div 0 0929-027 figure 27. dac-to -dac crosstalk
ad5304/ad5314/ad5324 data sheet rev. h | page 12 of 24 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer function. typical inl vs. code plots can be seen in figure 5, figure 6, and figure 7. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed mono- tonic by design. typical dnl vs. code plots can be seen in figure 8, figure 9, and figure 10. offset error this is a measure of the offset error of the dac and the output amplifier. it is expressed as a percentage of the full-scale range. gain error this is a measure of the span error of the dac. it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in decibels. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another dac. it is expressed in microvolts. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in decibels. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device when the dac output is not being written to ( sync held high). it is specified in nv-s and is measured with a worst- case change on the digital input pins (for example, from all 0s to all 1s or vice versa.) digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with the ldac bit set low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac and the thd is a measure of the harmonics present on the dac output. it is measured in decibels.
data sheet ad5304/ad5314/ad5324 rev. h | page 13 of 24 dac code gain error plus offset error output voltage negative offset error actual ideal negative offset error amplifier footroom (1mv) dead band co des 00929-028 figure 28. transfer functi on with negative offset actual ideal dac code positive offset output voltage gain error plus offset error 00929-029 figure 29. transfer function with positive offset
ad5304/ad5314/ad5324 data sheet rev. h | page 14 of 24 theory of operation functional description the ad5304/ad5314/ad5324 are quad, resistor-string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits, respectively. each contains four output buffer amplifiers and is written to via a 3-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 v/s. the four dacs share a single reference input pin. the devices have pro- grammable power-down modes, in which all dacs can be turned off completely with a high impedance output. digital-to-analog the architecture of one dac channel consists of a resistor-string dac followed by an output buffer amplifier. the voltage at the refin pin provides the reference voltage for the dac. figure 30 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by n ref out d v v 2 ? ? where d = decimal equivalent of the binary code that is loaded to the dac register: 0C255 for ad5304 (8 bits) 0C1023 for ad5314 (10 bits) 0C4095 for ad5324 (12 bits) n = dac resolution. refin output buffer amplifier resistor string dac register input register v out a 0 0929-030 figure 30. dac channel architecture resistor string the resistor string section is shown in figure 31. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. r r r r r to output amplifier 00929-031 figure 31. resistor string dac reference inputs there is a single reference input pin for the four dacs. the reference input is not buffered. the user can have a reference voltage as low as 0.25 v or as high as vdd because there is no restriction due to the headroom or footroom requirements of any reference amplifier. it is recommended to use a buffered reference in the external circuit (for example, ref192). the input impedance is typically 45 k. output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 v to v dd when the reference is v dd . it is capable of driving a load of 2 k to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in the plot in figure 15. the slew rate is 0.7 v/s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 s. power-on reset the ad5304/ad5314/ad5324 are provided with a power-on reset function, so that they power up in a defined state. the power-on state uses normal operation and an output voltage set to 0 v. both input and dac registers are filled with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up. serial interface the ad5304/ad5314/ad5324 are controlled over a versatile, 3-wire serial interface that operates at clock rates up to 30 mhz and are compatible with spi, qspi, microwire, and dsp interface standards.
data sheet ad5304/ad5314/ad5324 rev. h | page 15 of 24 bit15 (msb) a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 x x bit0 (lsb) pd ldac data bits 0 0929-032 figure 32. ad5304 input shift register contents bit15 (msb) bit0 (lsb) a1 a0 d7d8d9 d6 d5 d4 d3 d2 d1 d0 x x pd ldac data bits 00929-033 figure 33. ad5314 input shift register contents bit15 (msb) bit0 (lsb) a1 a0 d7d8d9 d10d11 d6 d5 d4 d3 d2 d1 d0 pd ldac data bits 00929-034 figure 34. ad5324 input shift register contents input shift register the input shift register is 16 bits wide. data is loaded into the device as a 16-bit word under the control of a serial clock input, sclk. see figure 2 for the timing diagram of this operation. the 16-bit word consists of four control bits followed by 8, 10, or 12 bits of dac data, depending on the device type. data is loaded msb first (bit 15) and the first two bits determine whether the data is for dac a, dac b, dac c, or dac d. bit 13 and bit 12 control the operating mode of the dac. bit 13 is pd , and deter- mines whether the part is in normal or power-down mode. bit 12 is ldac , and controls when dac registers and outputs are updated. table 6. address bits a1 a0 dac addressed 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d address and control bits pd 0: all four dacs go into power-down mode, consuming only 200 na @ 5 v. the dac outputs enter a high impedance state. 1: normal operation. ldac 0: all four dac registers and, therefore, all dac outputs updated simultaneously on completion of the write sequence. 1: only addressed input register is updated. there is no change in the content of the dac registers. the ad5324 uses all 12 bits of dac data; the ad5314 uses 10 bits and ignores the 2 lsb bits. the ad5304 uses eight bits and ignores the last four bits. the data format is straight binary, with all 0s corresponding to 0 v output and all 1s corresponding to full-scale output (v ref ? 1 lsb). the sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. data can be transferred into the device only while sync is low. to start the serial data transfer, take sync low, observing the minimum sync to sclk falling edge setup time, t 4 . after sync goes low, serial data shifts into the devices input shift register on the falling edges of sclk for 16 clock pulses. any data and clock pulses after the 16 th falling edge of sclk are ignored because the sclk and din input buffers are powered down. no further serial data transfer occurs until sync is taken high and low again. sync can be taken high after the falling edge of the 16 th sclk pulse, observing the minimum sclk falling edge to sync rising edge time, t 7 . after the end of the serial data transfer, data automatically transfers from the input shift register to the input register of the selected dac. if sync is taken high before the 16 th falling edge of sclk, the data transfer is aborted and the dac input registers are not updated. when data has been transferred into three of the dac input registers, all dac registers and all dac outputs are simultaneously updated by setting ldac low when writing to the remaining dac input register. low power serial interface to reduce the power consumption of the device even further, the interface fully powers up only when the device is being written to, that is, on the falling edge of sync . as soon as the 16-bit control word has been written to the part, the sclk and din input buffers are powered down. they power up again only following a falling edge of sync .
ad5304/ad5314/ad5324 data sheet rev. h | page 16 of 24 double-buffered interface the ad5304/ad5314/ad5324 dacs have double-buffered inter- faces consisting of two banks of registersinput registers and dac registers. the input register is directly connected to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac register contains the digital code used by the resistor string. access to the dac register is controlled by the ldac bit. when the ldac bit is set high, the dac register is latched and hence the input register can change state without affecting the contents of the dac register. however, when the ldac bit is set low, all dac registers are updated after a complete write sequence. this is useful if the user requires simultaneous updating of all dac outputs. the user can write to three of the input registers individually and then, by setting the ldac bit low when writing to the remaining dac input register, all outputs update simultaneously. these parts contain an extra feature whereby the dac register is not updated unless its input register has been updated since the last time that ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad5304/ad5314/ad5324, the part updates the dac register only if the input register has been changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. power-down mode the ad5304/ad5314/ad5324 have low power consumption, dissipating only 1.5 mw with a 3 v supply and 3 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into power-down mode, selected by a 0 on bit 13 ( pd ) of the control word. when the pd bit is set to 1, all dacs work normally with a typical power consumption of 600 a at 5 v (500 a at 3 v). however, in power-down mode, the supply current falls to 200 na at 5 v (80 na at 3 v) when all dacs are powered down. not only does the supply current drop, but also the output stage is internally switched from the output of the amplifier, making it open-circuit. this has the advantage that the output is three-stated while the part is in power-down mode, and provides a defined input condition for whatever is connected to the output of the dac amplifier. the output stage is illustrated in figure 35. the bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power- down mode is activated. however, the contents of the registers are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. this is the time from the falling edge of the 16 th sclk pulse to when the output voltage deviates from its power down voltage. see figure 22 for a plot. resistor string dac a mplifie r v out power-down circuitry 0 0929-035 figure 35. output stage during power-down microprocessor interfacing ad5304/ad5314/ad5324 to adsp-21xx figure 36 shows a serial interface between the ad5304/ad5314/ ad5324 and the adsp-21xx family. the adsp-21xx is set up to operate in the sport transmit alternate framing mode. the adsp-21xx sport is programmed through the sport control register and must be configured as follows: internal clock operation, active-low framing, and 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. the data is clocked out on each rising edge of the dsps serial clock and clocked into the ad5304/ad5314/ ad5324 on the falling edge of the dacs sclk. ad5304/ ad5314/ ad5324* adsp-21xx* *additional pins omitted for clarity. din dt sclk sclk sync tfs 0 0929-036 figure 36. ad5304/ad5314/ad5324 to adsp-21xx interface
data sheet ad5304/ad5314/ad5324 rev. h | page 17 of 24 ad5304/ad5314/ad5324 to 68hc11/68l11 interface figure 37 shows a serial interface between the ad5304/ad5314/ ad5324 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5304/ad5314/ad5324, while the mosi output drives the serial data line (din) of the dac. the sync signal is derived from a port line (pc7). the setup conditions for the correct operation of this interface are as follows: the 68hc11/68l11 is configured so that its cpol bit is a 0 and its cpha bit is a 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as above, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/ 68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5304/ ad5314/ad5324, pc7 is left low after the first eight bits are transferred, a second serial write operation is performed to the dac, and pc7 is taken high at the end of this procedure. ad5304/ ad5314/ ad5324* 68hc11/68l11* *additional pins omitted for clarity. sclk sck din mosi sync pc7 0 0929-037 figure 37. ad5304/ad5314/ad5324 to 68hc11/68l11 interface ad5304/ad5314/ad5324 to 80c51/80l51 interface figure 38 shows a serial interface between the ad5304/ad5314/ ad5324 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5304/ad5314/ad5324, while rxd drives the serial data line of the part. the sync signal is again derived from a bit-programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5304/ad5314/ ad5324, p3.3 is taken low. the 80c51/80l51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 outputs the serial data in a format that has the lsb first. the ad5304/ ad5314/ad5324 requires its data with the msb as the first bit received. the 80c51/80l51 transmit routine takes this into account. ad5304/ ad5314/ ad5324* 80c51/80l51* *additional pins omitted for clarity. sclk txd din rxd sync p3.3 0 0929-038 figure 38. ad5304/ad5314/ad5324 to 80c51/80l51 interface ad5304/ad5314/ad5324 to mi crowire interface figure 39 shows an interface between the ad5304/ad5314/ ad5324 and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the ad5304/ad5314/ad5324 on the rising edge of sk, which corresponds to the falling edge of the dacs sclk. ad5304/ ad5314/ ad5324* microwire* *additional pins omitted for clarity. sclk sk din so sync cs 0 0929-039 figure 39. ad5304/ad5314/ad5324 to microwire interface
ad5304/ad5314/ad5324 data sheet rev. h | page 18 of 24 applications information typical application circuit the ad5304/ad5314/ad5324 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 v to v dd . more typically, these devices are used with a fixed, precision reference voltage. suitable references for 5 v operation are the ad780 and ref192 (2.5 v references). for 2.5 v operation, a suitable external reference would be the ad589, a 1.23 v band gap reference. figure 40 shows a typical setup for the ad5304/ ad5314/ad5324 when using an external reference. ad5304/ad5314/ ad5324 v dd = 2.5v to 5.5 v sclk refin din sync v out a v out b v out c v out d gnd a0 serial interface v out v in external reference ad790/ref192 with v dd = 5v or ad589 with v dd = 2.5v 1f 0.1f 10f 00929-040 figure 40. ad5304/ad5314/ad5324 using external reference if an output range of 0 v to v dd is required, the simplest solution is to connect the reference input to v dd . as this supply is not very accurate and can be noisy, the ad5304/ad5314/ad5324 can be powered from the reference voltage; for example, using a 5 v reference such as the ref195. the ref195 can output a steady supply voltage for the ad5304/ad5314/ad5324. the current required from the ref195 is 600 a supply current and approxi- mately 112 a into the reference input. this is with no load on the dac outputs. when the dac outputs are loaded, the ref195 also needs to supply the current to the loads. the total current required (with a 10 k load on each output) is 712 a + 4 (5 v/10 k) = 2.70 ma the load regulation of the ref195 is typically 2 ppm/ma, resulting in an error of 5.4 ppm (27 v) for the 2.7 ma current drawn from it. this corresponds to a 0.0014 lsb error at eight bits and 0.022 lsb error at 12 bits. bipolar operation using the ad5304/ad5314/ad5324 the ad5304/ad5314/ad5324 have been designed for single supply operation, but a bipolar output range is also possible using the circuit in figure 41. this circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. ad5304 refin gnd v out a v out b v out c v out d serial interface din sclk sync v out v in gnd ref195 1f 0.1f 10f +6v to +16v v dd +5v ?5v 5v +5v ad820/ op295 r1 = 10k ? r2 = 10k ? 0 0929-041 figure 41. bipolar operation with the ad5304 the output voltage for any input code can be calculated as follows: )1/2( )()2/ ( rrrefin r1 r2r1 drefin v n out u uu where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. refin is the reference voltage input: refin = 5 v, r1 = r2 = 10 k v out = (10 d /2 n ) ? 5 v
data sheet ad5304/ad5314/ad5324 rev. h | page 19 of 24 opto-isolated interface for pr ocess control applications the ad5304/ad5314/ad5324 have a versatile 3-wire serial inter-face, making them ideal for generating accurate voltages in process control and industrial applications. due to noise, safety requirements, or distance, it might be necessary to isolate the ad5304/ad5314/ad5324 from the controller. this can easily be achieved by using opto-isolators, which provide isolation in excess of 3 kv. the actual data rate achieved is limited by the type of optocouplers chosen. the serial loading structure of the ad5304/ad5314/ad5324 makes them ideally suited for use in opto-isolated applications. figure 42 shows an opto-isolated interface to the ad5304 where din, sclk, and sync are driven from optocouplers. the power supply to the part also needs to be isolated. this is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5304. sclk din ad5304 sync gnd 5v regulator power v dd 10f 0.1f refin v dd 10k? 10k? 10k? din sync sclk v dd v dd v out a v out b v out c v out d 00929-042 figure 42. ad5304 in an opto-isolated interface decoding multiple ad5304/ad5314/ad5324s the sync pin on the ad5304/ad5314/ad5324 can be used in applications to decode a number of dacs. in this application, all the dacs in the system receive the same serial clock and serial data, but sync can only be active to one of the devices at any one time, allowing access to four channels in this 16-channel system. the 74hc139 is used as a 2-to-4-line decoder to address any of the dacs in the system. to prevent timing errors, the enable input must be brought to its inactive state while the coded address inputs are changing state. figure 43 shows a diagram of a typical setup for decoding multiple ad5304 devices in a system. 00929-043 74hc139 enable coded a ddress 1g 1a 1b dgnd 1y0 1y1 1y2 1y3 sclk din v cc v dd din sclk ad5304 sync din sclk ad5304 sync din sclk ad5304 sync din sclk ad5304 sync v out a v out b v out c v out d v out a v out b v out c v out d v out a v out b v out c v out d v out a v out b v out c v out d figure 43. decoding multiple ad5304 devices in a system ad5304/ad5314/ad5324 as a digitally programmable window detector a digitally programmable upper/lower limit detector using two dacs in the ad5304/ad5314/ad5324 is shown in figure 44. the upper and lower limits for the test are loaded to dac a and dac b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led indicates the fail condition. similarly, dac c and dac d can be used for window detection on a second v in signal. * additional pins omitted for clarity. 5v 1/2 cmp04 fail pass 1/6 74hc05 v ref sclk din v out a v dd 1/2 ad5304/ad5314/ ad5324* refin gnd 0.1f 10f 1k ? 1k? v in pass/fail din sclk sync sync v out b 00929-044 figure 44. window detection
ad5304/ad5314/ad5324 data sheet rev. h | page 20 of 24 power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5304/ad5314/ad5324 is mounted is designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5304/ad5314/ad5324 are in a system where multiple devices require an agnd-to-dgnd connection, the connection is made at one point only. the star ground point is established as close as possible to the device. the ad5304/ad5314/ad5324 has ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. the power supply lines of the ad5304/ad5314/ad5324 use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks are shielded with digital ground to avoid radiating noise to other parts of the board, and are never run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to a ground plane while signal traces are placed on the solder side. table 7. overview of ad53xx serial devices part no. resolution no. of dacs dnl interface settling time (s) package pins singles ad5300 8 1 0.25 spi 4 sot-23, msop 6, 8 ad5310 10 1 0.5 spi 6 sot-23, msop 6, 8 ad5320 12 1 1.0 spi 8 sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 sot-23, msop 6, 8 ad5311 10 1 0.5 2-wire 7 sot-23, msop 6, 8 ad5321 12 1 1.0 2-wire 8 sot-23, msop 6, 8 duals ad5302 8 2 0.25 spi 6 msop 8 ad5312 10 2 0.5 spi 7 msop 8 ad5322 12 2 1.0 spi 8 msop 8 ad5303 8 2 0.25 spi 6 tssop 16 ad5313 10 2 0.5 spi 7 tssop 16 ad5323 12 2 1.0 spi 8 tssop 16 quads ad5304 8 4 0.25 spi 6 msop, lfcsp 10 ad5314 10 4 0.5 spi 7 msop, lfcsp 10 ad5324 12 4 1.0 spi 8 msop, lfcsp 10 ad5305 8 4 0.25 2-wire 6 msop 10 ad5315 10 4 0.5 2-wire 7 msop 10 ad5325 12 4 1.0 2-wire 8 msop 10 ad5306 8 4 0.25 2-wire 6 tssop 16 ad5316 10 4 0.5 2-wire 7 tssop 16 ad5326 12 4 1.0 2-wire 8 tssop 16 ad5307 8 4 0.25 spi 6 tssop 16 ad5317 10 4 0.5 spi 7 tssop 16 ad5327 12 4 1.0 spi 8 tssop 16 octals ad5308 8 8 0.25 spi 6 tssop 16 ad5318 10 8 0.5 spi 7 tssop 16 ad5328 12 8 1.0 spi 8 tssop 16
data sheet ad5304/ad5314/ad5324 rev. h | page 21 of 24 table 8. overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time (s) additional pin functions package pins singles buf gain hben clr ad5330 8 0.25 1 6 ? ? ? tssop 20 ad5331 10 0.5 1 7 ? ? tssop 20 ad5340 12 1.0 1 8 ? ? ? tssop 24 ad5341 12 1.0 1 8 ? ? ? ? tssop 20 duals ad5332 8 0.25 2 6 ? tssop 20 ad5333 10 0.5 2 7 ? ? ? tssop 24 ad5342 12 1.0 2 8 ? ? ? tssop 28 ad5343 12 1.0 1 8 ? ? tssop 20 quads ad5334 8 0.25 2 6 ? ? tssop 24 ad5335 10 0.5 2 7 ? ? tssop 24 ad5336 10 0.5 4 7 ? ? tssop 28 ad5344 12 1.0 4 8 tssop 28
ad5304/ad5314/ad5324 data sheet rev. h | page 22 of 24 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 45. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 121009-a top view 10 1 6 5 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 46. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm x 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters
data sheet ad5304/ad5314/ad5324 rev. h | page 23 of 24 ordering guide model 1, 2 temperature range package description package option branding ad5304arm C40c to +105c 10-lead msop rm-10 dba ad5304arm-reel7 C40c to +105c 10-lead msop rm-10 dba ad5304armz C40c to +105c 10-lead msop rm-10 d9w ad5304armz-reel7 C40c to +105c 10-lead msop rm-10 d9w ad5304acpz-reel7 C40c to +105c 10-lead lfcsp_wd cp-10-9 dba# ad5304brm C40c to +105c 10-lead msop rm-10 dbb ad5304brm-reel C40c to +105c 10-lead msop rm-10 dbb ad5304brm-reel7 C40c to +105c 10-lead msop rm-10 dbb ad5304brmz C40c to +105c 10-lead msop rm-10 dbb# ad5304brmz-reel C40c to +105c 10-lead msop rm-10 dbb# ad5304brmz-reel7 C40c to +105c 10-lead msop rm-10 dbb# ad5304bcpz-reel7 C40c to +105c 10-lead lfcsp_wd cp-10-9 dbb# ad5314acpz-reel7 C40c to +105c 10-lead lfcsp_wd cp-10-9 dca# ad5314arm C40c to +105c 10-lead msop rm-10 dca ad5314arm-reel7 C40c to +105c 10-lead msop rm-10 dca ad5314armz C40c to +105c 10-lead msop rm-10 dca# ad5314armz-reel7 C40c to +105c 10-lead msop rm-10 dca# ad5314warmz-reel7 C40c to +105c 10-lead msop rm-10 dca# ad5314bcpz-reel7 C40c to +105c 10-lead lfcsp_wd cp-10-9 dcb# ad5314brm C40c to +105c 10-lead msop rm-10 dcb ad5314brm-reel C40c to +105c 10-lead msop rm-10 dcb ad5314brm-reel7 C40c to +105c 10-lead msop rm-10 dcb ad5314brmz C40c to +105c 10-lead msop rm-10 dcb# ad5314brmz-reel C40c to +105c 10-lead msop rm-10 dcb# ad5314brmz-reel7 C40c to +105c 10-lead msop rm-10 dcb# ad5324acpz-reel7 C40c to +105c 10-lead lfcsp_wd cp-10-9 dda# ad5324arm C40c to +105c 10-lead msop rm-10 dda ad5324arm-reel7 C40c to +105c 10-lead msop rm-10 dda ad5324armz C40c to +105c 10-lead msop rm-10 d8f ad5324armz-reel7 C40c to +105c 10-lead msop rm-10 d8f ad5324bcpz-reel7 C40c to +105c 10-lead lfcsp_wd cp-10-9 ddb# ad5324brm C40c to +105c 10-lead msop rm-10 ddb ad5324brm-reel C40c to +105c 10-lead msop rm-10 ddb ad5324brm-reel7 C40c to +105c 10-lead msop rm-10 ddb AD5324BRMZ C40c to +105c 10-lead msop rm-10 ddb# AD5324BRMZ-reel C40c to +105c 10-lead msop rm-10 ddb# AD5324BRMZ-reel7 C40c to +105c 10-lead msop rm-10 ddb# 1 z = rohs compliant part; # denotes lead-free product can be top or bottom marked. 2 w = qualified for auto motive applications. automotive products the ad5314warmz-reel7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that this automotive model may have specifications that differ from the commercial models; theref ore designers should review the specifications section of this data sheet carefully. only the automotive grade product shown is ava ilable for use in automotive applications. contact your local analog devices account representative for specific product ordering informat ion and to obtain the specific automotive reliability reports for this model.
ad5304/ad5314/ad5324 data sheet rev. h | page 24 of 24 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00929-0-9/11(h)

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